From an environmental point of view, a greater demand for reduced energy has arisen in recent years. In electronic devices, such as portable phones and digital cameras, reducing power consumption is a requisite for extending battery usage time.
From such a point of view, power supply devices have used switching regulators that provide higher efficiency and enable miniaturization. Synchronous rectification boosting PFM-controlled type power supply devices are known as switching regulators with which high efficiency can be achieved at light loads.
Synchronous rectification boosting PFM-controlled type power supply devices operate by transitioning successively to three modes A, B and C as shown in FIGS. 8 to 10, for example.
The power supply device has an input side terminal Tin, an inductor L, a switch SWL (NMOS transistor), a switch SWH (PMOS transistor), an output side capacitor C, an output side terminal Tout, and a comparator UO.
Here, comparator UO compares output voltage VBoost and target voltage VBSET.
The power supply device generates control signals HCNT and LCNT that respectively turn switches SWH and SWL on and off, respectively, based on the comparison result by comparator UO.
However, because switches SWL and SWH are MOSFETs, parasitic diodes DL and DH are respectively present.
The power supply device successively switches between modes A, B and C as shown below.
Mode A
In mode A, as shown in FIG. 8, switch SWL is on, and switch SWH is off in accordance with control signals HCNT and LCNT.
Current flows from input side terminal Tin through inductor L and between D (drain)—S (source) of switch SWL to ground. Energy is stored in inductor L by this. Then, when the current flowing to switch SWL exceeds a certain value, the target energy is determined to have been stored in inductor L, and control signals HCNT and LCNT are switched to transition to mode B.
Mode B
In mode B, as shown in FIG. 9, switch SWH is on, and switch SWL is off in accordance with control signals HCNT and LCNT.
Current flows to the output side according to the energy stored in inductor L, and output voltage VBoost is boosted by this.
Then, when the energy stored in inductor L is exhausted and the voltage at terminal SW falls below output voltage VBoost, reverse current flow from the output voltage VBoost side to input side terminal Tin starts. The power supply device switches control signals HCNT and LCNT to transition to mode C when the reverse current flow is sensed.
Mode C
In mode C, as shown in FIG. 10, switch SWH is off and switch SWL is off, in accordance with control signals HCNT and LCNT.
Output side capacitor C is discharged by load Io connected to output side terminal Tout, and output voltage VBoost falls because of this.
Then, output voltage VBoost falls below target voltage VBSET, and output VSETdet of comparator UO is switched from low level to high level.
The power supply device switches control signals HCNT and LCNT to transition to mode A when switching of output VSETdet to high level is sensed.
In this way, output voltage VBoost is boosted to an approximately constant value, as shown in FIG. 11, by repetition of the transition between modes A/B/C described above by the power supply device.
However, with the power supply device described above, a problem exists as below under conditions where input voltage VIN is higher than the target voltage VBSET for output voltage VBoost.
(Problem 1: VIN>Vbset+VHon)
When input voltage VIN is higher than a voltage in which diode voltage VHon of parasitic diode DH is added to target voltage VBSET for output voltage VBoost, because parasitic diode DH is always on, output voltage VBoost cannot be lower than target voltage VBSET.
For this reason, in mode C described above, the condition that “voltage VBoost falls below target voltage VBSET” cannot be satisfied, and transition to modes A and B will not occur.
In this case, output voltage VBoost falls only by the amount of diode voltage VHon of diode DH from input voltage VIN. The problem is that, in this state, the power supply device will always lose power that is voltage VHon multiplied by load current Io, and the power consumption will be high.
(Problem 2: VBoost+VHon≧VIN≧VBSET)
As shown in FIG. 12, when input voltage VIN is higher than target voltage VBSET for voltage VBoost and lower than the voltage of diode voltage VHon of parasitic diode DH added to voltage VBoost, transitioning successively to modes A, B and C will occur.
In this case, in mode B, output voltage VBoost rises to a voltage approximately identical to voltage VIN, and transition to mode C occurs. After the transition to mode C, output voltage VBoost falls to target voltage VBSET for voltage VBoost from near input voltage VIN because of the discharge of capacitor C. Then, when comparator UO senses that output voltage VBoost has fallen below target voltage VBSET, control to transition to mode A is provided.
In this way, a voltage ripple occurs in output voltage VBoost approximately equal to a voltage width with input voltage VIN as the upper limit and target voltage VBSET for output voltage VBoost as the lower limit. The closer input voltage VIN is to the voltage (VBoost+VHon), the greater the voltage ripple becomes, and at its maximum, is a voltage approximately equal to diode voltage VHon.
Generally, the voltage ripple in the power supply device will be 600-700 mV, which is a large value. Such a large voltage ripple is undesirable for circuitry using output voltage VBoost as the source voltage.
And depending on the power supply device construction, malfunctioning of the circuitry because of the voltage ripple is also a concern.
The present invention was devised in consideration of this situation. Its objective is to provide a boost circuit and power supply device that reduces power consumption and prevents malfunctioning when the input voltage is higher than the target voltage for the output voltage.